A typical computing system is composed of multiple processors and various memory components in electrical communication with each other allowing for communication of data therebetween. A typical processing system, which may include one or more of a plurality of processors, must be coordinated so the interfacing with the memory device is done on a timely basis. For example, timing signals must be properly coordinated so the processing device requests and receives data in proper synchronization with the memory device. Another example of an element that must be tuned is a skew rate.
Previously, fine tuning a memory device with a processing device, such as an application specific integrated circuit (ASIC) is performed by hand. Using an oscilloscope, signal strengths and signal timings are measured between the processing device and the memory. Based on these signal measurements, control values within the processing device, such as resistive or capacitive loads, hardware logic, firmware or any other implementation for executing operations, are thereby adjusted. Once the processing device is provided with new parameters, further measurements are then taken on new signals between the processing device and the memory. Once again, based on these measurements, re-calculations are made for elements within the processing device. The iterative process is repeated until the interface between the memory and the processing device is finely tuned. The current approach is extremely inefficient and time consuming. The manual calculations are labor intensive and utilize a significant amount of time for one or more individuals to perform all the calculations in the iterative process to effectuate the tuning. Furthermore, when a processing device is utilized with different memories for different applications, the processing device may need to be specifically tuned for each of the memory devices. Therefore, simply because a processing device is tuned for a first memory, if that processing device is then implemented using a second memory in a second system, the tuning process must be redone. As such, this further limits efficiency with regards to utilizing a particular processing device in different processing environments or systems.
Therefore, there exists a need for a method and apparatus to automatically fine tune a memory interface with respect to a particular memory.